Data line driving methods, data line driving units, source drivers, panel driving devices and display devices

ABSTRACT

The present disclosure discloses data line driving methods, data line driving units, source drivers, panel driving devices and display devices capable of reducing power consumption due to charge and discharge of the parasitic capacitance on the data line. The data line driving method comprises steps of: determining whether current time is within a blanking period of time between two frames; outputting a preset voltage signal to the data line on a condition that the current time is within the blanking period of time and outputting a gray-scale voltage signal to the data line on a condition that the current time is not within the blanking period of time.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims the benefit of Chinese Patent Application No.201510395777.7 filed on Jul. 6, 2015 and entitled “DATA LINE DRIVINGMETHODS, DATA LINE DRIVING UNITS, SOURCE DRIVERS, PANEL DRIVING DEVICESAND DISPLAY DEVICES”, which is incorporated herein by reference inentirety.

FIELD OF INVENTION

The present disclosure relates to the field of display, and particularto data line driving methods, data line driving units, source drivers,panel driving devices and display devices.

BACKGROUND

Liquid crystal displays (LCD) have various advantages, such as zeroradiation, low power consumption, small heat radiation, small size,accurate image reproduction, sharp character display, etc., andcurrently have become the most popular display products.

A displaying process of LCD is shown as follows: the source drivingintegrated circuit (IC) supplies the data lines with a gray-scalevoltage corresponding to luminance (i.e., GAMMA voltage), and then thescanning lines supply on-state voltage to turn on thin film transistor(TFT) switches. The voltage at the corresponding data line is loaded topixel electrodes through the data line and the TFT switch to charge theliquid crystal capacitance Cps to form a gray-scale and thus to displayimages. At the same time, there are many parasitic capacitances on thewhole data line, and an end electrode of each capacitance (such as Cx1,Cx2, Cd0, Cpd in FIG. 1) is connected to the data line. Therefore, whenthe data line charges and discharges the capacitance of liquid crystalCps, it also charges and discharges these parasitic capacitances,resulting in unnecessary power consumption.

At present, dielectric anisotropy and optical anisotropy of the liquidcrystal molecule are utilized to obtain different displaying grayscales. In order to prevent liquid crystal molecules from beingsolidified for being at a certain voltage for a long period of time, anAC driving mode is adopted to maintain characteristics of the liquidcrystal molecules. However, the AC driving mode means that the data linevoltage will change constantly, which will lead to continuous chargingand discharging of the above-mentioned parasitic capacitances. This willgenerate leakage current on the data lines, increase load of thesource-driven chip and cost more power consumption.

SUMMARY OF THE INVENTION

The present disclosure provides data line driving methods, data linedriving units, source drivers, panel driving devices and display devicescapable of reducing power consumption due to charging and discharging ofparasitic capacitances on a data line.

In order to at least solve the above technical problems, embodiments ofthe present disclosure utilize the following technical solutions.

The present disclosure provides a data line driving method comprisingsteps of: determining whether current time is within a blanking periodof time between two frames; outputting a preset voltage signal to thedata line on a condition that the current time is within the blankingperiod of time and outputting a gray-scale voltage signal to the dataline on a condition that the current time is not within the blankingperiod of time.

Alternatively, the preset voltage signal is a common voltage signal.

Alternatively, the determining step comprises determining, by a dataenabling signal, whether the current time is within the blanking periodof time between two frames.

Alternatively, the outputting step comprises: generating a controlsignal for connecting an input terminal of the data line to the commonvoltage circuit on a condition that the current time is within theblanking period of time and generating a control signal for connectingthe input terminal of the data line to a source driving circuit on acondition that the current time is not within the blanking period oftime; and connecting the input terminal of the data line to the commonvoltage circuit or the source driving circuit according to the controlsignal.

The present disclosure provides a data line driving unit comprising: adetermining unit configured for determining whether current time iswithin a blanking period of time between two frames; a switching unitconfigured for connecting an input terminal of the data line to a presetvoltage signal generating circuit on a condition that the determiningunit determines that the current time is within the blanking period oftime, and connecting the input terminal of the data line to a sourcedriving circuit on a condition that the determining unit determines thatthe current time is not within the blanking period of time.

Alternatively, the determining unit is further configured for generatinga control signal for connecting the input terminal of the data line tothe preset voltage signal generating circuit on a condition that it isdetermined that the current time is within the blanking period of time,and generating a control signal for connecting the input terminal of thedata line to the source driving circuit on a condition that the currenttime is not within the blanking period of time.

Alternatively, the preset voltage signal generating circuit is a commonvoltage circuit.

Alternatively, a control terminal of the switching unit is connected tothe determining unit, a first input terminal of the switching unit isconnected to the source driving circuit, a second input terminal of theswitching unit is connected to the common voltage circuit, and an outputterminal of the switching unit is connected to the input terminal of thedata line; and the switching unit receives the control signal from thedetermining unit and connects the input terminal of the data line to thesource driving circuit or the common voltage circuit according to thecontrol signal.

Alternatively, the determining unit determines, by a data enablingsignal, whether the current time is within the blanking period of timebetween the two frames.

The present disclosure provides a source driver comprising a sourcedriving circuit and a preset voltage signal generating circuit andfurther comprising: a determining unit configured for determiningwhether current time is within a blanking period of time between twoframes; and a switching unit configured for connecting an input terminalof the data line to the preset voltage signal generating circuit on acondition that the determining unit determines that the current time iswithin the blanking period of time, and connecting the input terminal ofthe data line to the source driving circuit on a condition that thedetermining unit determines that the current time is not within theblanking period of time.

Alternatively, the determination unit is a timing controller.

Alternatively, the determining unit determines, by a data enablingsignal, whether the current time is within a blanking period of timebetween two frames.

Alternatively, the preset voltage signal generating circuit is a commonvoltage circuit.

The present disclosure further provides a panel driving devicecomprising a data line driving unit according to any one of the abovementioned embodiments or a source driver according to any one of theabove mentioned embodiments.

The present disclosure further provides another panel driving deviceincluding a timing controller and a source driver, wherein the sourcedriver includes a source driving circuit and a preset voltage signalgenerating circuit; the timing controller is configured for determiningwhether current time is within a blanking period of time between twoframes, generating a control signal for connecting an input terminal ofthe data line to the preset voltage signal generating circuit on acondition that the current time is within the blanking period of time,and generating a control signal for connecting the input terminal of thedata line to the source driving circuit on a condition that the currenttime is not within the blanking period of time; the source driverfurther comprises a switching unit configured for receiving the controlsignal outputted by the timing controller and selecting to connect theinput terminal of the dada line to the preset voltage signal generatingcircuit or the source driving circuit according to the control signal.

The present disclosure also provides a display device comprising a paneldriving device according to any one of the above mentioned embodiments.

The present disclosure provides data line driving methods, data linedriving units, source drivers, panel driving devices and displaydevices. By only outputting a gray scale voltage signal to data linesduring an active time interval for loading display data to displayregions and outputting a preset voltage signal such as a common voltagesignal to the data lines during the remaining blanking period of time(i.e. the blank time regions), the data line is maintained at a fixedvoltage level during the whole blanking period of time so as to avoidcharging and discharging of the parasitical capacitances. Thus, theleakage current on the data lines is almost zero so as to decrease powerconsumption of the panel. Since the output preset voltage signal on thedata line is not actually applied to the capacitances of the liquidcrystal during the blanking period of time between two frames, it willnot affect the characteristic of the liquid crystal and can't bring anydisadvantageous influence on display effect.

DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions of theembodiments of the present disclosure, the drawings which are requiredto be used in the embodiments will be briefly described hereinafter. Itwill be apparent that the drawings described below are only someembodiments of the present disclosure, It will be apparent to thoseskilled in the art that other drawings may be acquired from of theaccompanying drawings without departing from the inventive labors.

FIG. 1 is a schematic view of an equivalent circuit for pixel parasiticcapacitances of a LCD provided by prior art;

FIG. 2 is a schematic view of a blanking period of time and an activetime interval output by the source driver in an embodiment of thepresent disclosure;

FIG. 3 is a schematic view of a 1 Hz resting driving in the IGZO TFTaccording to an embodiment of the present disclosure;

FIG. 4 is a flowchart of a data line driving method according to anembodiment of the present disclosure;

FIG. 5 is a flowchart of a data line driving method according to anembodiment of the present disclosure;

FIG. 6 is a schematic view of generating a control signal according toan embodiment of the present disclosure;

FIG. 7 is a block diagram of a data line driving unit according to anembodiment of the present disclosure;

FIG. 8 is a schematic view of principle of the data line driving unitaccording to an embodiment of the present disclosure;

FIG. 9 is a schematic view of principle of the source driver accordingto an embodiment of the present disclosure;

FIG. 10 is a schematic view of another source driver according to anembodiment of the present disclosure.

REFERENCE NUMERALS

-   -   10—display screen, 11—display area, 12 non-display area,        21—processor, 22—timing controller, 23—source driver, 24—source        driving circuit, 25—common voltage circuit, 26—controllable        switch, 27—data line input terminal, 100—determining unit,        200—switching unit.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

In order to facilitate understanding of concepts of the blanking periodof time and so on related to the technical solution of the presentdisclosure, the present embodiment briefly describes the relatedcontents.

In the LCD technology, a source driving circuit directly outputs data todata lines, and the data outputted on each data line includes valid data(Vadr) and blanking data, which are distinguished according to numbersof clock pulses. As particularly shown in FIG. 2, a reference sign of 10represents a LCD screen, a reference sign of 11 represents a displayarea at center of the display screen, and a reference sign of 12represents a non-display area at periphery of the display screen. Avertical synchronizing signal and a horizontal synchronizing signal areregularly used signals in the display field, wherein the verticalsynchronizing signal is used to control a length of one frame of pictureand a length of its active time interval corresponds to the data lengthof one frame of picture. When the signal is loaded, the active timeinterval corresponds to display area at center of the display screen 10,i.e. valid data in the data line signals are loaded in the display area11. A blanking period of time (also known as invalid time interval) ofthe vertical synchronizing signal corresponds to a length of timebetween two frames. When the signal is loaded, the blanking period oftime is corresponding to the non-display area 12 of the display panel10, i.e., blanking data is loaded in the non-display area 12. Theblanking period of time in the present embodiment corresponds to avertical front porch (VFP) or a vertical back porch (VBP) in thevertical synchronizing signal.

As shown in FIG. 3, when an Indium Gallium Zinc oxide (IGZO) TFT is usedfor resting driving of 1 Hz (or other low frequency driving), if a stillpicture is displayed, the frame is updated only during the first 1/60second, and the screen is displayed in a resting state for the remaining59/60 seconds. In the resting state, neither the processor 21 updatesframe data to a timing controller (Tcon, also known as a timer controlregister) 22, nor could the timing controller 22 updates frame data tothe source driver 23. That is to say, during this period of 59/60seconds, the output of the source driver 23 is within the Blankingperiod of time.

In the above design, the source driver 23 outputs a pixel gray-scalevoltage signal regardless of being in the frame updating state or theresting state. When the output is within a blanking period of timebetween the two frames, despite the data lines providing a gray-scalevoltage signal, it is not displayed on the panel (corresponding to thenon-display area 12 at this time), i.e. the liquid crystal capacitancesare not charged or discharged. At this time, the voltage level of theentire data line keeps changing, resulting in that the parasiticcapacitances on the entire data line is in a state of being continuouslycharge and discharged. Therefore, a certain amount of leakage current isgenerated in the data line and unnecessary power consumption isintroduced.

With respect to the above problems, the present disclosure adjusts thevoltage signal on the data line to be a preset voltage signal such as acommon voltage signal during the blanking period of time between twoframes until a valid data is output. The data line is maintained at afixed voltage level during the whole blanking period of time so as toavoid charging and discharging of the parasitical capacitances. Thus,the leakage current on the data line is zero. Meanwhile, since such adriving during the blanking period of time is not actually applied tothe capacitances of the liquid crystal during the blanking period oftime, it will not affect the characteristic of the liquid crystal andcan't bring any disadvantageous influence on display effect.

The technical solution of embodiments of the present disclosure would beclearly and completely illustrated in conjunction with accompanydrawings of the embodiments of the present disclosure. It is obviousthat the illustrated embodiments are only a part of the presentdisclosure and are not all of the embodiments.

An embodiment of the present disclosure provides a data line drivingmethod comprising steps of: determining whether current time is within ablanking period of time between two frames; outputting a preset voltagesignal to the data line if the current time is within the blankingperiod of time; and outputting a gray-scale voltage signal to the dataline if the current time is not within the blanking period of time.

In the present embodiment, the blanking period of time is defined as atime interval between two frames, i.e. a time period from an end ofloading a frame to a start of loading next frame. Alternatively, thepresent embodiment can determine, by a data enabling signal, whether thecurrent time is within the blanking period of time between two frames,as will be described in detail in the following description. The presetvoltage signal in the present embodiment is a voltage signal with aconstant voltage level, which may be a common voltage signal or otherconstant voltage signal.

The present embodiment outputs a preset voltage signal to the data linesduring the whole blanking period of time between two frames, so that thedata line is maintained at a fixed voltage level so as to avoid chargingand discharging of the parasitical capacitances. Thus, the leakagecurrent on the data line is zero. Meanwhile, since such a preset voltagesignal during the blanking period of time is not actually applied to thecapacitances of the liquid crystal, it will not affect thecharacteristic of the liquid crystal and the display effect.

The data line driving method according to the present embodiment will bedescribed in detail with reference to the accompanying drawings in whichthe preset voltage signal is taken as an example of the common voltagesignal. As shown in FIG. 4, the present embodiment employs a data linedriving method including the following steps:

Step S101, determining whether the current time is within a blankingperiod of time. If the current time is within the blanking period oftime, the step S102 is executed. If the current time is not within theblanking period of time, the step S103 is executed.

Step S102, outputting a common voltage signal to the data line.

Step S103, outputting a gray-scale voltage signal to the data line.

Since the time period between the end of a frame and the start of nextframe is the blanking period of time and there is a verticalsynchronizing signal at the start of each frame, step S101 can determinewhether the current time is within the blanking period of time betweenthe two frames by the vertical synchronizing signal. In addition, thepresent embodiment does not exclude use of other signals and othermethods to determine the blanking period of time. The result of thedetermination in the step S101 may directly function as a trigger signalfor selecting to execute the step S102 or the step S103 at the nextstep. In addition, the trigger signal may be generated based on thedetermination result of the step S101 to control the next step ofselecting whether to execute the step S102 or the step S103. The stepS102 outputs the common voltage signal to the data line by connectingthe input terminal of the data line to the common voltage circuit. Thestep of S103 outputs the gray-scale voltage signal to the data line byconnecting the input terminal of the data line to the source drivecircuit.

The data line driving method provided by the present embodiment isparticularly shown in FIG. 5. As shown in FIG. 5, the data line drivingmethod comprises the following steps: S201, determining whether thecurrent time is within the blanking period of time between two frames;S202, generating a control signal for connecting the input terminal ofthe data line to the common voltage circuit if the current time iswithin the blanking period of time, and generating a control signal forconnecting the input terminal of the data line to a source drivingcircuit if the current time is not within the blanking period of time;and S203, connecting the input terminal of the data line to the sourcedriving circuit or the common voltage circuit according to the controlsignal.

Specifically, a video card is responsible for processing image material(data) sent from CPU into a form recognizable by the display and thensending to the display screen. In order for the data in the video cardto be displayed correctly, it is needed to generate in a timingcontroller 22 a display data signal and a control signal for the driverthrough conversion. Since the output signal of the timing controller 22is mainly generated by a counter, its timing depends on two factors,namely, the data structure and the display mode of the image signal. Asshown in FIG. 6, the timing controller 22 may determine the setVBP/VFP/valid data to identify size and position of the valid pixelarea, thereby to generate a data enabling signal (DE signal) forcontrolling a timing of the data output by the data line. Therefore, aslong as a determining instruction is added to the timing controller 22,it is possible to realize the function of the determining unit todetermine whether the current time is within the blanking period oftime. The specific determining process is shown as follows.

For example, the 1 Hz resting driving for IGZO TFT is taken as anexample. When the frame needs to be refreshed, the timing controller 22outputs a DE signal for controlling the data line to output a datasignal voltage (i.e., a gray-scale voltage signal). Each line willoutput a data enabling signal with a high level. Thus, as long as it ismonitored whether the data enabling signal DE is at high level duringtwo consecutive clock cycles, it may be determined whether the currenttime is within the blanking period of time. If the data enabling signalis at high level during the two consecutive clock cycles, it may bedetermined that it needs to be switched to data signal; otherwise, thecommon voltage signal is output. Of course, a functional module may bedirectly designed to determine whether the current time is within theblanking period of time, so that the timing controller will not beneeded.

The data line driving method provided by the present embodimentdetermines whether to output a common voltage signal or to output apixel voltage to the data lines according to whether the current time iswithin the blanking period of time. If the current time is within theblanking period of time between two frames, the signal on the data linesare adjusted to be the common voltage signal VCOM; otherwise, the grayscale voltage signal is output. Thus, the data line is maintained at afixed voltage level during the whole blanking period of time between twoframes so as to avoid charging and discharging of the parasiticalcapacitances of the data lines and to decrease power consumption of thepanel. Meanwhile, since the loading of the common voltage signal is notactually applied to the capacitance of the liquid crystal during theblanking period of time between two frames, it will not affect thecharacteristic of the liquid crystal and the display effect.

As shown in FIG. 7, the embodiment of the present disclosure alsoprovides data line driving unit comprising: a determining unit 100configured for determining whether current time is within a blankingperiod of time between two frames; a switching unit 200 configured forconnecting an input terminal of the data line to a preset voltage signalgenerating circuit (e.g. a common voltage circuit) on a condition thatthe determining unit 100 determines that the current time is within theblanking period of time, and connecting the input terminal of the dataline to a source driving circuit on a condition that the determiningunit 100 determines that the current time is not within the blankingperiod of time. The data line driving unit may decrease powerconsumption of the panel; and meanwhile, it won't affect thecharacteristic of the liquid crystal and the display effect.

The determining unit 100 of the present embodiment is further configuredfor generating a control signal for connecting the input terminal of thedata line to the preset voltage signal generating circuit if it isdetermined that the current time is within the blanking period of time,and generating a control signal for connecting the input terminal of thedata line to the source driving circuit if the current time is notwithin the blanking period of time. Alternatively, the determining unit100 determines, by the data enabling signal, whether the current time iswithin the blanking period of time between the two frames. In aparticular implementation, the determining unit 100 may be comparator orother logic devices or a determining instruction may be directly addedto the timing controller 22 to implement the function of the determiningunit 100.

The preset voltage signal generating circuit is configured to generate avoltage signal with a constant voltage level. Preferably, the presetvoltage signal generating circuit is a common voltage circuit or acommon voltage generating circuit inside the source driver, or a commonvoltage circuit on the panel. The common voltage circuit is taken as anexample to be illustrated in detail. In the present embodiment, acontrol terminal of the switching unit 200 is connected to thedetermining unit 100, a first input terminal of the switching unit 200is connected to the source driving circuit, a second input terminal ofthe switching unit is connected to the common voltage circuit, and anoutput terminal of the switching unit is connected to the input terminalof the data line. The switching unit 200 receives the control signal ofthe determining unit and connects the input terminal of the data line tothe source driving circuit or the common voltage circuit according tothe control signal.

In the present embodiment, the data line driving unit adjusts the signalon the data line to be the common voltage signal VCOM during theblanking period of time between the two frames, and the phenomenon ofcharging and discharging of the parasitic capacitances on the data linecan be neglected so as to decrease power consumption of the panelwithout affecting the display effect. The present disclosure put nolimitation on how to determine whether the current time is within theblanking period of time between the two frames and how to output theVCOM voltage to the data line, which may be any one of theimplementations known to those skilled in the art.

In one alternative implementation, the input terminal of the data lineis provided with a switching unit such as a controllable switch, asparticularly shown in FIG. 8. An input terminal 27 of each data line isconnected to an output terminal of the controllable switch 26. The firstinput terminal of the controllable switch 26 is connected to acorresponding output terminal of the source driving circuit 24 and thesecond input terminal of the controllable switch 26 is connected to acommon voltage circuit 25 (which may be a common voltage output terminalof the source driver 23 or a common electrode line). The controlterminal of the controllable switch 26 receives control signals from thedetermining unit 100. The controllable switch 26 selects to connect theinput terminal 27 of the data line to the source driving circuit 24 orthe common voltage circuit 25 according to the control signal.

When it is determined that the current output of the source driver 23 iswithin the blanking period of time, the determining unit 100 supplies atrigger signal to trigger the controllable switch 26 to be switched, sothat the data line is connected to the common voltage circuit 25 toobtain and output the common voltage VCOM to decrease power consumption.When it is determined that the current output of the source driver 23 ina valid data output stage (not within the blanking period of time), thetrigger signal is again supplied to trigger the controllable switch 26to switch to connect the data line to the source drive circuit 24. Thedata line receives and outputs the gray-scale voltage signal from thesource driving circuit 24 to realize display.

An embodiment of the present disclosure further provides a sourcedriver. As shown in FIG. 9, the source driver comprises a source drivingcircuit and a preset voltage signal generating circuit. The sourcedriver further comprises: a determining unit 100 configured fordetermining whether current time is within a blanking period of timebetween two frames; and a switching unit 200 configured for connectingan input terminal of the data line to the preset voltage signalgenerating circuit when the determining unit determines that the currenttime is within the blanking period of time (the result of which is tooutput a preset voltage signal to the data line), and configured forconnecting the input terminal of the data line to the source drivingcircuit when the determining unit 100 determines that the current timeis not within the blanking period of time (the result of which is tooutput the gray scale voltage signal to the data line). Alternatively,the determining unit 100 determines, by the data enabling signal,whether the current time is within the blanking period of time betweenthe two frames. The function of the determining unit 100 may beintegrated into the timing controller internal to the source driver andthe determining unit may be a separate functional module as shown inFIG. 9.

An embodiment of the present disclosure further provides a panel drivingdevice comprising the data line driving unit according to any one of theabove mentioned items or the source driver according to any one of theabove mention items. The source driver provided by the embodiments ofthe present disclosure has lower power consumption withoutdisadvantageously affecting the display effect.

An embodiment of the present disclosure further provides another paneldriving device. As shown in FIG. 10, the panel driving device comprisesa timing controller 22 and a source driver 23, wherein the source driver23 includes a source driving circuit and a preset voltage signalgenerating circuit. The timing controller is configured for determiningwhether current time is within a blanking period of time between twoframes, generating a control signal for connecting the input terminal ofthe data line to the preset voltage signal generating circuit when thecurrent time is within the blanking period of time, and generating acontrol signal for connecting the input terminal of the data line to thesource driving circuit when the current time is not within the blankingperiod of time. The source driver 23 further comprises a switching unit200 for receiving the control signal outputted by the timing controller22 and selecting to connect the input terminal of the dada line to thepreset voltage signal generating circuit or the source driving circuitaccording to the control signal.

In the present embodiment, the timing controller is located outside thesource driver, and the source driver includes only the switching unit.The timing controller realizes the function of the determining unit todetermine whether the current time is within the blanking period oftime, and to generate a control signal for controlling the switchingunit to switch. The control signal includes information about whetherthe current time is within the blanking period of time between the twoframe pictures, and the switching unit realizes the switching.

The source driver provided by the present embodiment outputs thecorresponding common voltage signal to the data lines when the currenttime is within the blanking period of time and outputs the commonvoltage signal to the data line when the current time is not within theblanking period of time, which avoids charging and discharging of theparasitical capacitance to decrease power consumption of the panel, andalso bring any disadvantageous effects to the display effect.

An embodiment of the present disclosure further provides a displaydevice provided with the data line driving unit according to any one ofthe above mentioned items, or the source driver as mentioned above orthe panel driving device as mentioned above. The display device savespower and decreases power consumption, and at the same time may get ahigher display quality by reducing the influence of the parasiticcapacitance on the display effect. The display device may be a productor a component having a display function such as a liquid crystal panel,an electronic paper, an OLED panel, a mobile phone, a tablet computer, atelevision set, a display, a notebook computer, a digital photo frameand a navigator.

Various embodiments of the present specification are described in aprogressive manner, and identical and similar parts between the variousembodiments are referred to each other. Each embodiment will focus onthe differences from the other embodiments. In particular, for themethod embodiment, since it is substantially similar to the methodembodiment, the description is relatively simple, and the correlationcan be seen in part of the description of the embodiment of the method.

It will be appreciated by those of ordinary skill in the art that all ora portion of the flow in the method of the embodiments as describedabove may be accomplished by a computer program that instructs theassociated hardware to be stored in a computer-readable storage medium;when executed, a flow of embodiments of the above-described methods maybe included. The storage medium may be a magnetic disk, an optical disk,a read-only memory (ROM), or a random access memory (RAM).

While the disclosure has been described in detail, it should beunderstood that the disclosure is not limited thereto. Any changes orsubstitutions which may occur to those skilled in the art fall withinthe scope of the present disclosure. Therefore, the scope of the presentdisclosure should be determined by the scope of the claims.

1. A data line driving method, comprising steps of: determining whethercurrent time is within a blanking period of time between two frames;outputting a preset voltage signal to the data line on a condition thatthe current time is within the blanking period of time and outputting agray-scale voltage signal to the data line on a condition that thecurrent time is not within the blanking period of time.
 2. The data linedriving method according to claim 1, wherein the preset voltage signalis a common voltage signal.
 3. The data line driving method according toclaim 1, wherein the determining step comprises: determining, by a dataenabling signal, whether the current time is within the blanking periodof time between two frames.
 4. The data line driving method according toclaim 2, wherein the outputting step comprises: generating a controlsignal for connecting an input terminal of the data line to a commonvoltage circuit on a condition that the current time is within theblanking period of time and generating a control signal for connectingthe input terminal of the data line to a source driving circuit on acondition that the current time is not within the blanking period oftime; and connecting the input terminal of the data line to the commonvoltage circuit or the source driving circuit according to the controlsignal.
 5. A data line driving unit comprising: a determining unitconfigured for determining whether current time is within a blankingperiod of time between two frames; a switching unit configured forconnecting an input terminal of the data line to a preset voltage signalgenerating circuit on a condition that the determining unit determinesthat the current time is within the blanking period of time, andconnecting the input terminal of the data line to a source drivingcircuit on a condition that the determining unit determines that thecurrent time is not within the blanking period of time.
 6. The data linedriving unit according to claim 5, wherein the determining unit isfurther configured for generating a control signal for connecting theinput terminal of the data line to the preset voltage signal generatingcircuit on the condition that the current time is within the blankingperiod of time, and generating a control signal for connecting the inputterminal of the data line to the source driving circuit on the conditionthat the current time is not within the blanking period of time.
 7. Thedata line driving unit according to claim 5, wherein the preset voltagesignal generating circuit is a common voltage circuit.
 8. The data linedriving unit according to claim 7, wherein a control terminal of theswitching unit is connected to the determining unit, a first inputterminal of the switching unit is connected to the source drivingcircuit, a second input terminal of the switching unit is connected tothe common voltage circuit, and an output terminal of the switching unitis connected to the input terminal of the data line; and the switchingunit receives the control signal from the determining unit and connectsthe input terminal of the data line to the common voltage circuit or thesource driving circuit according to the control signal.
 9. The data linedriving unit according to claim 5, wherein the determining unitdetermines, by a data enabling signal, whether the current time iswithin the blanking period of time between the two frames.
 10. A sourcedriver comprising: a source driving circuit; a preset voltage signalgenerating circuit; a determining unit configured for determiningwhether current time is within a blanking period of time between twoframes; and a switching unit configured for connecting an input terminalof the data line to the preset voltage signal generating circuit on acondition that the determining unit determines that the current time iswithin the blanking period of time, and connecting the input terminal ofthe data line to the source driving circuit on a condition that thedetermining unit determines that the current time is not within theblanking period of time.
 11. The source driver according to claim 10,wherein the determination unit is a timing controller.
 12. The sourcedriver according to claim 10, wherein the determining unit determines,by a data enabling signal, whether the current time is within a blankingperiod of time between two frames.
 13. The source driver according toclaim 10, wherein the preset voltage signal generating circuit is acommon voltage circuit.
 14. (canceled)
 15. (canceled)
 16. (canceled)